We want to evaluate thermal behavior of 3D circuits as a function of the partitioning strategy (stacked memory, interposer, IPs distribution, etc…) The work will consist in using thermal simulation tools, defining a methodology to use these tools in the context of 3D integrated circuits (TSVs, Monolithic Integration, etc…). Starting from simulations and discussion with process teams, the goal is to evaluate thermal dissipation and extrapolate design rules / partitioning constraints to optimize it. Required background : know-how in mixed-signal design (Cadence Virtuoso & Encounter, Mentor Eldo & Calibre) Basic know-how of Matlab / Scilab Autonomy, team spirit

This position is open until it is filled.

Département: Département Architectures Conception et Logiciels Embarqués (LIST-LETI)
Laboratory: Laboratoire Intégration Silicium des Architectures Numériques
Start Date: 01-04-2015
ECA Code: PsD-DRT-14-0040
Contact: olivier.billoint<στο>cea.fr